LVDS Translator ams4005

by amstark.
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2 layer board of 0.44x0.30 inches (11.07x7.57 mm).
Shared on September 30th, 2013 12:45.

LVDS to single ended 3v LVTTL buffer. 3.3v power, gnd, and singled ended signal on one side and LVDS pair on the other. Developed for Virtex 7 FPGA interface. Driver - SN65LVDS1DBVR Receiver - SN65LVDT2DBVR

This design is licensed under the GNU Public License 3.

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